DRAM (Dynamic Random Access Memory) is desirable over SRAM (Static Random Access Memory) in many situations because DRAM arrays can be denser and DRAM devices require less power to operate. As semiconductor device sizes continue to decrease (for example, toward the 22 nanometer node, and smaller), single gate devices begin to experience performance degradation, such as short channel effects. Accordingly, there is a trend toward using multiple gate field effect transistor devices (e.g., MuGFET). Some conventional DRAM devices employ a planar transistor with a gate beneath the channel and a word line above the channel. However, these arrangements exhibit relatively low performance and can only be arranged in low-density arrays.
A challenge facing DRAM improvement is the reduction of operating power even lower than what it is currently employed. This is at least partly due to the phenomenon of leakage. For example, when threshold voltage of a fin-type field effect transistor (FinFET) DRAM device is reduced too far, leakage becomes a significant concern. The threshold voltage of the fin of the FinFET retards leakage of stored charge out of the capacitance structure of the DRAM. Leakage increases as threshold voltage decreases, thereby requiring more frequent updating of the capacitance structure of the DRAM.
However, it is desirable in some circumstances to have a low threshold voltage, because a lower threshold voltage permits a lower wordline voltage to be utilized with the DRAM device. Put another way, when the threshold voltage is kept high to prevent undesirable leakage, the wordline voltage during read and write operations must also be high to overcome the threshold voltage. Since the wordline voltage is directly related to the operating power required to drive a DRAM device, leakage is generally in conflict with lowering the operating power.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.